Version 12.1.0.0 and higher
--------------------------
SPD reading/writing is not supported on the Intel Core X-series Processor Family (Skylake-X) due to a lack of the necessary "Intel Core X-series processor family Datasheet Volume 2" document.

Version 9.5.0.0 and higher
--------------------------
Since version 9.5.0.0 XMP Enhancer is capable of accessing DRAM controller configuration registers of Intel processors to read DRAM frequency and timings to create a XMP profile. Unfortunately, not all Intel processors are fully supported due to the lack of technical documentation.

* 2nd Gen "Sandy Bridge" Desktop & Mobile Intel Core  full support;
* 3rd Gen "Ivy Bridge" Desktop & Mobile Intel Core  full support;
* 3rd Gen Desktop & Server Intel Core and Xeon LGA2011  full support;
* 4th Gen Desktop & Server Intel Core and Xeon LGA2011-v2  full support;
* 4th Gen "Haswell" Desktop & Mobile Intel Core  tWR and tWTR timings are not read;
* 5th Gen Desktop & Server Intel Core and Xeon LGA2011-v3  tRRD_L is not read. The current DRAM controller frequency is not detected and forced to be displayed at 1067 MHz.

Since version 9.8.2.0
* 6th Gen "Skylake" Desktop & Mobile Intel CPUs with DDR4 MC mode - full support;
* 6th Gen "Skylake" Desktop & Mobile Intel CPUs with DDR3 MC mode - tWR & tWTR are not read.
